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SNVS441F – JANUARY 2007 – REVISED FEBRUAY 2013
APPLICATION AND REGISTER INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
CAPACITOR SELECTION
The LP5521 requires 4 external capacitors for proper operation (C IN = C OUT = 1 μ F, C FLY1 = C FLY2 = 470 nF).
Surface-mount multi-layer ceramic capacitors are recommended. These capacitors are small, inexpensive and
have very low equivalent series resistance (ESR < 20 m ? typ.). Tantalum capacitors, OS-CON capacitors, and
aluminum electrolytic capacitors are not recommended for use with the LP5521 due to their high ESR, as
compared to ceramic capacitors.
For most applications, ceramic capacitors with X7R or X5R temperature characteristic are preferred for use with
the LP5521. These capacitors have tight capacitance tolerance (as good as ±10%) and hold their value over
temperature (X7R: ±15% over -55°C to 125°C; X5R: ±15% over -55°C to 85°C).
Capacitors with Y5V or Z5U temperature characteristic are generally not recommended for use with the LP5521.
Capacitors with these temperature characteristics typically have wide capacitance tolerance (+80%, -20%) and
vary significantly over temperature (Y5V: +22%, -82% over -30°C to +85°C range; Z5U: +22%, -56% over +10°C
to +85°C range). Under some conditions, a nominal 1 μ F Y5V or Z5U capacitor could have a capacitance of only
0.1 μ F. Such detrimental deviation is likely to cause Y5V and Z5U capacitors to fail to meet the minimum
capacitance requirements of the LP5521.
The minimum voltage rating acceptable for all capacitors is 6.3V. The recommended voltage rating of the output
capacitor is 10V to account for DC bias capacitance losses.
Some ceramic capacitors, especially those in small packages, exhibit a strong capacitance reduction
with the increased applied voltage (DC bias effect). The capacitance value can fall below half of the
nominal capacitance. Choose output and input capacitor with DC bias voltage effect better than –50% at
5V voltage (0.5 μ F at 5V).
LIST OF RECOMMENDED EXTERNAL COMPONENTS
Model
Type
Vendor
Voltage Rating
Size inch (mm)
1 μ F for C OUT and C IN
C1005X5R1A105K
ECJ0EB1A105M
ECJUVBPA105M
Ceramic X5R
Ceramic X5R
Ceramic X5R, array of two
TDK
Panasonic
Panasonic
10 V
10 V
10 V
0402 (1005)
0402 (1005)
0504
470 nF for C FLY1-2
C1005X5R1A474K
ECJ0EB0J474K
Ceramic X5R
Ceramic X5R
TDK
Panasonic
10 V
10 V
0402 (1005)
0402 (1005)
LEDs
User Defined
PROGRAM LOAD AND EXECUTION EXAMPLE
Startup Device and Configure Device to SRAM Write Mode:
?
?
?
?
?
?
?
Supply e.g. 3.6V to VDD
Supply e.g. 1.8V to EN
Wait 1 ms (startup delay)
Generate 32 kHz clock to CLK_32K pin
Write to address 00H 0100 0000b (enable LP5521)
Wait 500 μ s (startup delay)
Write to address 01H 0001 0000b (Configure R channel into "Load program to SRAM" mode)
Program Load to SRAM (see figure below):
?
?
?
Write to address 10H 0000 0011b (1st ramp command 8 MSB)
Write to address 11H 0111 1111b (1st ramp command 8 LSB)
Write to address 12H 0100 1101b (1st wait command 8 MSB)
Copyright ? 2007–2013, Texas Instruments Incorporated
Product Folder Links: LP5521
27
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